Apparatus and method for booting a system

ABSTRACT

A method and apparatus for booting a system are provided. The apparatus may comprise a boot block and a baseboard management controller coupled together in the system. The baseboard management controller may be configured to receive a request from the boot block for a basic input/output system image; determine at least one location to access the basic input/output system image; and obtain the basic input/output system image from the at least one location.

BACKGROUND OF THE RELATED ART

This section is intended to introduce the reader to various aspects ofart, which may be related to various aspects of the present inventionthat are described and/or claimed below. This discussion is believed tobe helpful in providing the reader with background information tofacilitate a better understanding of the various aspects of the presentinvention. Accordingly, it should be understood that these statementsare to be read in this light, and not as admissions of prior art.

Generally, a processor-based system includes Basic Input/Output System(“BIOS”) code to initialize the system in a boot process. The BIOS isutilized when a system is initially turned on to perform a series ofinstructions to test the components and to load the Operating System(“O/S”). The BIOS may include different portions of basic software toprovide the initial set-up and configuration of the system.

The BIOS may be upgraded or updated by loading another version. Thecontents of the BIOS or a portion of the BIOS may be stored in areprogrammable non-volatile memory, such as a FLASH memory or anon-volatile Random Access Memory (NVRAM), to allow the contents of theBIOS to be changed. The act of changing the contents of non-volatilememory is often called “flashing” the memory. Typically, for the BIOS tobe upgraded, support personnel often access the system at the system'ssite. This method of upgrading the BIOS is time consuming for thesupport personnel and increases the cost of supporting the system.

Further, to prevent the corruption of the BIOS, the flashing of the BIOSmay include different security measures, such as maintaining redundantcopies of the BIOS in the system. The redundant copies of the BIOSconsume additional memory space within the system, which is merelyutilized for security and back-up purposes. Along with consumingadditional memory space, these redundant copies of the BIOS may conflictwith each other and further complicate support issues for the system.

SUMMARY OF THE INVENTION

Certain aspects commensurate in scope with the originally claimedinvention are set forth below. It should be understood that theseaspects are presented merely to provide the reader with a brief summaryof certain forms the invention might take and that these aspects are notintended to limit the scope of the invention. Indeed, the invention mayencompass a variety of aspects that may not be set forth below.

In accordance with one aspect of the present invention, a system andmethod for booting a system is provided. The system comprises a bootblock and a baseboard management controller. The baseboard managementcontroller is configured to receive a request from the boot block for abasic input/output system image; determine a location to access thebasic input/output system image; and obtain the basic input/outputsystem image from the location.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention are apparent upon reading thefollowing detailed description with reference to the drawings in which:

FIG. 1 is a block diagram illustrating a network in accordance with anexemplary embodiment of the present invention;

FIG. 2 is a block diagram illustrating an exemplary computer system inthe network of FIG. 1 in accordance with one embodiment of the presentinvention;

FIG. 3 is a functional block diagram of an exemplary baseboardmanagement controller of FIG. 2 constructed in accordance with anembodiment of the present invention;

FIG. 4 is a functional block diagram of exemplary servers in the networkof FIG. 1 in accordance with one embodiment of the present invention;

FIG. 5 is a process flow diagram illustrating an exemplary boot blockand baseboard management controller of FIG. 2 in accordance withembodiments of the present invention; and

FIG. 5.1 illustrates a method in accordance with an exemplary embodimentof the present invention.

FIG. 6 is a process flow diagram illustrating the use of the policy codein the exemplary baseboard management controller of FIG. 3 in accordancewith embodiments of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments of the present invention will bedescribed below. In an effort to provide a concise description of theseembodiments, not all features of an actual implementation are describedin the specification. It should be appreciated that in the developmentof any such actual implementation, as in any engineering or designproject, numerous implementation-specific decisions may be made toachieve the developers' specific goals, such as compliance withsystem-related and business-related constraints, which may vary from oneimplementation to another. Moreover, it should be appreciated that sucha development effort might be complex and time consuming, but wouldnevertheless be a routine undertaking of design, fabrication, andmanufacture for those of ordinary skill having the benefit of thisdisclosure.

The techniques disclosed herein provide an improved approach for bootinga system. Specifically, the techniques described herein include a bootblock and baseboard management controller that are utilized to boot asystem. The baseboard management controller is configured to receive arequest from the boot block for a BIOS image; determine a location toaccess the BIOS image; and obtain the BIOS image from the location. Byutilizing the baseboard management controller, the system may boot fromBIOS images in different locations. Further, the baseboard managementcontroller may utilize policy code to manage the access to differentlocations that include the BIOS images. Thus, the system may conservememory space by booting from BIOS images that are external to the systemand provide a simplified process for managing the versions of BIOSimages provided to the system.

Referring initially to FIG. 1, a block diagram of a network architectureis illustrated and designated using a reference numeral 10. A networkdevice 20 may be connected to a plurality of client systems 22, 24 and26, which may take the form of personal computer systems, thin clients,workstations, desktop personal computer (“PC”), a notebook PC, a tabletPC, a personal digital assistant (“PDA”), or the like. The networkdevice 20 may be connected to many different client systems, asdesignated by the variable “n.” The magnitude of “n” may be a functionof the computing power of the network device 20. The network device 20may include a router, switch, hub, bridge, and/or other suitable similarnetwork devices.

The network device 20 may be connected via a network 30, which mayinclude a combination of other hubs, switches, routers, or the like.While the network 30 is illustrated as being either a local area network(“LAN”), a wide area network (“WAN”), or a metropolitan area network(“MAN”), those skilled in the art will appreciate that the network 30may assume other forms and may even provide network connectivity throughthe Internet. As described below, the network architecture 10 mayinclude other servers as well, which may be dispersed geographicallyand/or logically with respect to each other to support client systems inother locations.

The network 30 may connect the network device 20 to another networkdevice 40, which is similar to the network device 40. The network device40 may be connected to one or more servers 42, 44, and 46 along with anexternal memory 48 via a network 50. As illustrated in FIG. 1, thenetwork 50, which may include a LAN, a WAN, a MAN, or other networkconfiguration, may be used to connect the server systems 42, 44 and 46and the external memory 48 to the network device 40. The network device40 may additionally be connected to the Internet 60, which may beconnected to another network device 70. The network device 70 also maybe connected to one or more client systems 72, 74 and 76, which may becomputer systems, for example.

In the network architecture 10, the client systems 22, 24, 26, 72, 74and 76 and the servers 42, 44, and 46 may communicate with each other toperform various tasks or operations. For example, the servers 42, 44 and46 may provide applications and information to the client systems 22,24, 26, 72, 74 and 76. Similarly, the external memory 48 may providedata storage for the client systems 22, 24, 26, 72, 74 and 76 and theservers 42, 44, and 46. Accordingly, it should be appreciated that eachof the client systems 22, 24, 26, 72, 74 and 76 and the servers 42, 44,and 46 may be configured with various components and utilize variousapplications.

FIG. 2 is a block diagram illustrating an exemplary computer system inaccordance with embodiments of the present invention. For exemplarypurposes, the computer system is referred to as the server 42. It shouldbe understood, however, that the computer system is merely for exemplarypurposes, as the client systems 22, 24, 26, 72, 74 and 76 and servers 44and 46 may also include these various components. The architecture ofthe server 42 is given for purposes of illustration only, as computersystems in which the present teachings are applicable may includeadditional components or a subset of the components illustrated in FIG.2.

The server 42 may include a processor complex 102, which may include aplurality of central processing units (“CPUs”). For instance, theprocessor may be an Intel Xeon, AMD Opteron, and the like. A core logicchipset 104, which may manage a variety of functions on behalf of theprocessor complex 102, may be connected to the processor complex 102 viaa processor bus 103.

The core logic chipset 104 may be connected via memory bus 105 to asystem random access memory (“RAM”) 106, which may comprise staticrandom access memory (“SRAM”), dynamic random access memory (“DRAM”),synchronous DRAM (“SDRAM”) or other suitable memories. The memory may bea shared system memory to hold memory resident files. Further, thesystem RAM 106 may include a shadow BIOS 107, which is a copy of a BIOSimage utilized by the processor complex 102 to complete the boot orinitialization process, as discussed below. A video graphics controller110 may be connected to the core logic chipset 104 via a video bus 108to provide a signal that produces a display image on a video display112.

A bus 109, such as a peripheral component interface (“PCI”) bus,registered PCI (“PCI-X”) or the like, may connect the core logic chipsetto a variety of system devices, such as a network interface card 122 anda PCI/PCI bridge 124. The network interface card 122 may providecommunication capability to the server 42 via a communication bus 119.The communication bus 119 may be connected to other computer systems, asdiscussed above. The PCI/PCI bridge 124 may provide capacity foradditional PCI devices on a PCI bus 117.

A PCI/SCSI bus adapter 115 may provide access to SCSI devices, such as adisk drive 130 and a tape drive 132, via a SCSI bus 131. A PCI/ATAcontroller 118 may provide access to additional devices such as a diskdrive 128 and a CD ROM drive 134. A PCI/EISA/LPC bridge 116 may provideaccess to system devices such as a read only memory basic input/outputsystem (“ROM BIOS”) 140, a non-volatile memory 142 (such as flash memoryor the like), a modem 120 or the like via a bus 113. The modem 120 mayprovide communication access via a phone line 121. Also, the ROM BIOS140 may include BIOS code or a portion of the BIOS code. The BIOS codemay be divided into two portions, such as a boot block 143 and a BIOSimage 144, which are discussed below in greater detail. An input/outputcontroller 126, which may be connected to the bus 113 may provide accessto system devices such as a floppy disk drive 150, a serial port 152 areal time clock (“RTC”) 154, a CD ROM drive 145, a keyboard 146, a mouse148 and the like.

A baseboard management controller (“BMC”) 111 may be connected to thebus 109 to perform system management and status operations. Forinstance, the BMC 111 may manage the environmental functions for theserver 42, receive and log event data for the server 42, manage sensorinterfaces, and provide access to the network 50 via the communicationbus 114.

To communicate with other components and systems, the BMC 111 may becoupled to internal components via the bus 109, the NIC 122 via a bus123, and the network 50 via a communication bus 114. From thesedifferent connections, the BMC 111 may communicate with other componentsregardless of the operational state of the O/S of the server 42. Forexample, the BMC 111 may communicate with the boot block 143 independentfrom the processor complex 102, which may be executing the O/S or may beshutdown. Because of this independent operation, the BMC 111 may beutilized by the boot block 143 as part of the boot process. The bootprocess may include a power-on self test, which performs softwareinstructions to allow the computer to begin the process of verifyingcomponents and loading the configuration for the components. In the bootprocess, the boot block 143 may verify the operation of specificcomponents and utilize the BMC 111 to load the BIOS image. The BIOSimage may then be utilized to complete the boot process. Thus, the bootblock 143 may initialize the server 42 until sufficient system RAM 106is available to accommodate the shadow BIOS 107, which may be obtainedby the BMC 111.

Beneficially, the use of the BMC 111 by the boot block 143 may enablethe server 42 to obtain a BIOS image from one or more locations, whichmay be local to and/or remote from the server 42. To obtain the BIOSimage, the boot block 143 may provide a request to the BMC 111 for aBIOS image being requested. The request may specify a version or afamily of the BIOS image. Then, the BMC 111 may obtain the BIOS image,which may be the BIOS image 144 or another BIOS image that may be localor external to the server 42. That is, the BMC 111 may obtain the BIOSimage from different locations, internal and external to the server 42.Once the BIOS is obtained, the boot block 143 may validate and completethe boot process by utilizing the BIOS image, which is loaded intosystem RAM 106 as a shadow BIOS 107.

As an example, the boot block 143 may initialize a portion of the systemRAM 106 to support the shadow BIOS. The boot block 143 may communicatewith the BMC 111 to obtain the BIOS image. To determine the appropriatelocation of the BIOS image, the BMC 111 may execute a policy sequence orcode that defines one or more locations that store the BIOS image.Accordingly, the BMC 111 may utilize its components to access the BIOSimage from local or remote locations. Then, the BMC 111 may provide theBIOS image to the boot block 143 for validation and verification of theBIOS image. Once the BIOS image is validated, the BIOS image may beloaded into the system RAM 106 to complete the initialization of theserver 42.

An exemplary BMC 111 is shown in greater detail in FIG. 3. FIG. 3illustrates a functional block diagram of an exemplary BMC 111constructed in accordance with an embodiment of the present invention.The components of the BMC 111 may be implemented as hardware, such asapplication specific integrated circuit (“ASIC”) or field gate arrays(“FGAs”), and/or software, such as routines or code to be executed by aprocessor. Those skilled in the art will appreciate that implementationdetails, such as deciding which functional aspects of BMC 111 areimplemented in hardware or software, are matters of design choice.

For purposes of describing the BMC 111 clearly, the BMC 111 is describedas being implemented as a single ASIC, which may be incorporated intothe server 42. As shown above, systems may be connected directly orindirectly to the BMC 111 through its network connection, which is morefully described below. Systems may also interface with the BMC 111through additional communications interfaces, such as a modem or USBports.

The BMC 111 may be implemented so that it is powered and capable ofoperation regardless of the operational status of the server 42. Thisindependent operation allows the BMC 111 to be utilized in the bootprocess to communicate with other systems or external memories, such asexternal memory 48.

The BMC 111 may include a processor 160 along with various logiccomponents to provide different interaction with the components of theserver 42. For instance, the processor 160 provides general control andfunctions as a management processor for the BMC 111. The processor 160may be implemented as a 32-bit RISC processor, but other processorimplementations may be employed as well. The processor 160 isoperatively coupled to a timer module 162 and an interrupt controller164 via a peripheral bus 166.

In one exemplary embodiment, a memory controller 168 is operativelycoupled to the processor 160 via an internal local bus 170. Further, thememory controller 168 is operatively coupled to dedicated memory 172,such as battery-backed SRAM or flash memory. However, other types ofmemory may also be utilized, which may include SDRAM, ROM, NVRAM or anyother appropriate type of memory. Within the dedicated memory 172 may bepolicy code 174. The policy code 174 may be a software routine thatincludes a listing of devices and an order of the devices to access fora BIOS image.

The processor 160 is operatively coupled to the other functional modules(and possibly many sub-modules) of the BMC 111 via an internal local bus170. Those of ordinary skill in the field will appreciate that theinternal local bus 170 facilitates communication between and among thelogical components of the BMC 111. For instance, an address translationand bridging (“ATB”) unit 176 may be operatively coupled to the internallocal bus 170 and to the bus 109. The ATB unit 176 provides access tothe bus 109 for the different logic components of the BMC 111. Also, asideband NIC interface 178 may be utilized to communicate with the NIC122.

FIG. 5.1 shows a method in accordance with an exemplary embodiment ofthe present invention.

Further, the BMC 111 may include communication interfaces that can beemployed to establish out-of-band communication sessions for the BMC111. One such communication interface is a UART interface 180, which isoperatively coupled to internal local bus 170. The exemplary UARTinterface 180 may include two standard 16550 UARTs, each of which mayprovide a separate serial communication interface via an RS-232interface or the Intelligent Chassis Management Bus (“ICMB”) interface.Another such communication interface is a USB interface 182, which isoperatively coupled to the internal local bus 170. The USB interface 182may be coupled to a USB host controller (not shown). Further, a NetworkInterface Card (“NIC”) 184, which is operatively coupled to the internallocal bus 170, provides another external communication interface betweenthe BMC 111 and network 50. The NIC 184 may include a MAC (Media AccessController), inbound and outbound FIFOs, a DMA engine to transferpackets automatically to and from memory, an external PHY, typicalmagnetics and connectors to couple the PHY to the wire that serves asthe transmission media to the network 50.

Another functionality provided by the BMC 111 is to provide the hardwareinfrastructure to implement control and monitoring functions in theserver 42 as dictated by the processor 160. To perform thisfunctionality, the slave instrumentation module 186 may include variouscomponents and logic. For instance, the slave instrumentation module 186may include an automatic server recovery (“ASR”) controller thatoperates to respond automatically to catastrophic failures of the server42 and a general purpose input/output module (“GPIO”) that provides aversatile communication interface. A JTAG master may also be utilized toperform a wide range of control functions on the server 42. Further, anI²C master may be utilized to control a plurality of independent I²Cserial channels. The slave instrumentation module 186 may also includesystem support logic to provide a variety of housekeeping and securityfunctions for the server 42, such as providing the EISA bus ID, flashROM support, ECC support, hot spare boot support, system post monitorsupport, floppy write protect, SMI base security measures, open hooddetection and the like.

Beneficially, by utilizing the policy code 174 within the BMC 111, theboot process for the server 42 may be modified to access differentdevices or systems to load the BIOS image. That is, the boot block 143may utilize the policy code 174 to manage the access to differentlocations while the server 42 is being booted. In this configuration,the BIOS image does not have to be local to the server 42, but may belocated in external memory 48 remote from the server 42. More details ofthe use of the BMC 111 in the server 42 are described in relation toFIG. 4, which is discussed below.

FIG. 4 illustrates a functional block diagram of exemplary servers inthe network of FIG. 1 in accordance with one embodiment of the presentinvention. Referring briefly to FIG. 1, recall that the servers 42, 44and 46 along with the external memory 48 are coupled together via anetwork 50. Each of these servers 42, 44 and 46 may include a boot block143, shadow BIOS 107 in the system RAM 106, and a BMC 111. The bootblock 143 may use the BMC 111 to access a first BIOS image 196 or asecond BIOS image 198 in the external memory 48 to be loaded into therespective server 42, 44 and 46. By downloading one of the BIOS images196 and 198, a single instance of the BIOS image 196 or 198 may beloaded into multiple systems, such as the servers 42, 44 and 46. Inaddition, the cost of maintaining a large flash ROM on each server 42,44 and 46 may be reduced because the BIOS images 196 and 198 are locatedin the external memory 48.

Accordingly, various code and components of the present embodiment mayoperate in a similar manner to those discussed above in FIGS. 1-3. Forinstance, the boot block 143, which may be referred to individually asboot blocks 143 ₁, 143 ₂, and 143 _(N), and shadow BIOS 107, which maybe referred to individually as shadow BIOSs 107 ₁, 107 ₂, and 107 _(N),may operate as discussed above. Similarly, the processor complex 102,which may be referred to individually as processor complexes 102 ₁, 102₂, and 102 _(N), the BIOS ROM 140, which may be referred to individuallyas BIOS ROMs 140 ₁, 140 ₂, and 140 _(N), the system RAM 106, which maybe referred to individually as system RAMs 106 ₁, 106 ₂, and 106 _(N),and the BMC 111, which may be referred to individually as BMCs 111 ₁,111 ₂, and 111 _(N), may also operate as discussed above.

In FIG. 4, each of the servers 42, 44 and 46 may load different BIOSimages 196 and 198 as part of the boot process on each of the servers42, 44 and 46. The first BIOS image 196 and the second BIOS image 198are shown as part of the external memory 48. The BIOS images 196 and 198may be different versions of a family of BIOS images or BIOS images fordifferent types of systems. As an example of the boot process, the bootblock 143 ₁ communicates with the BMC 111 ₁ to access the first BIOSimage 196. Then, the external memory 48 may provide the first BIOS image196 to the server 42 for validation by the boot block 143 ₁, and forexecution by the processor complex 102 ₁. Once validated, the shadowBIOS 107 ₁ may be loaded in the system RAM 106 ₁, to complete the bootprocess. Similarly, the boot block 143 ₂ communicates with the BMC 111 ₂to access the first BIOS image 196, which results in the shadow BIOS 107₂ being loaded in the system RAM 106 ₂. However, the boot block 143 _(N)communicates with the BMC 111 _(N) to access the second BIOS image 198,which results in the shadow BIOS 107 _(N) being loaded in the system RAM106 _(N).

Accordingly, one or more of the BIOS images 196 and 198 may be utilizedby each of the servers 42, 44 and 46 to load the respective shadow BIOSs107 that complete the initialization for each of the servers 42, 44 and46. As an example, the shadow BIOS 107 ₁ may be a copy of the BIOS image196, which is located in the system RAM 106 ₁. The shadow BIOS 107 ₁ maybe executed by the processor complex 102 ₁ to load the O/S 192 ₁ andthen the applications 194 ₁. During the boot process, the boot block 143may complete the initialization process by obtaining the first BIOSimage 196 from the external memory 48 by utilizing the BMC 111, which isremotely located from the server 42. Similarly, the shadow BIOS 107 ₂may be utilized to load the O/S 192 ₂ and then the applications 194 ₂,while the shadow BIOS 107 _(N) may be utilized to load the O/S 192 _(N)and the applications 194 _(N).

Beneficially, by utilizing the BMC 111 to access BIOS images 196 and 198from the external memory 48, one or more systems may be uniformlyinitialized and/or upgraded with new BIOS images. For instance, thistechnique may allow a single instance of a BIOS image to be utilized bymultiple servers. Specifically, as noted above, a BIOS image that islocated in the external memory 48 may be utilized to provide the sameversion of a BIOS image for multiple systems, such as servers 42 and 44.This allows support personnel to modify the BIOS image in multiplesystems with a single instance of the BIOS image. As a result of thistechnique, the support personnel does not have to travel to the locationfor each system or individually upgrade each system

In addition, by having a centralized BIOS image, such as the BIOS images196 and 198, the memory space consumed with a local copy or multiplecopies within a system may also be removed. That is, the cost associatedwith providing memory for maintaining the BIOS image on the system alongwith the associated redundancy and backup versions may be reducedbecause the BIOS image portion of the BIOS code may be located externalto the system. For instance, with a centralized BIOS image, the bootblock 143 for each server 42, 44 and 46 may download the appropriateBIOS image from external memory 48. A copy of the BIOS image would nothave to be locally stored on each of the servers 42, 44 and 46. In fact,the BIOS image in the external memory 48 may even be geographicallydistributed from each of the servers 42, 44 and 46. However, forredundancy purposes multiple copies are generally stored on the system,a single copy would be utilized to provide a back-up version of the BIOSimage, not multiple local copies. The boot process is further discussedin greater detail in FIGS. 5 and 6 below.

FIG. 5 is a process flow diagram illustrating the use of the exemplaryboot block 143 and BMC 111 of FIG. 2 in accordance with embodiments ofthe present invention. The process flow diagram is generally referred toby reference numeral 200. The process flow diagram 200 may be bestunderstood by concurrently viewing FIGS. 1-4. In the process flowdiagram 200, the boot block 143 may communicate with the BMC 111 toobtain a BIOS image for the system. The BMC 111 may utilize the policycode 174 to determine the location of the BIOS image to be accessed forthe system. That is, the boot block 143 may utilize the BMC 111 tomanage the access and procurement of the BIOS image from memory that isexternal or local to the system.

The process begins at block 202. At block 204, the boot block 143initializes the system RAM 106 within the system, which may be theserver 42. The initialization process may include determining whetherspecific components of the system are corrupt. The boot block 143 mayrepair or flag components that are corrupt. Then, the boot block 143 mayrequest a BIOS image from the BMC 111, as shown in block 206. Therequest may include an indication of the version of the BIOS image, typeof the BIOS image, the family of the BIOS image, or other suitableinformation to indicate the version of the BIOS image to be loaded.

In blocks 208-212, the BMC 111 may obtain the BIOS image. At block 208,the BMC 111 may utilize the policy code 174 in the BMC 111 to determinethe location of the BIOS image, which may be one of the BIOS images 196or 198. Then, at block 210, the BMC 111 may obtain the BIOS image. Toobtain the BIOS image, the BMC 111 may utilize different components toaccess the BIOS image, such as the USB interface 182 and/or the NIC 184.At block 210, the BMC 111 may download the BIOS image from the locationthat is designated by the policy code 174. Once the BIOS image has beenaccessed, the BIOS image may be loaded into the system RAM 106 by theBMC 111, as shown in block 212.

In blocks 214-222, the boot block 143 may verify the load of the BIOSimage, validate the BIOS image obtained by the BMC 111, and continue theboot or initialization process. At block 214, the boot block 143 maydetermine if the BIOS image is loaded into the system RAM 106. If theBIOS image is not loaded, then the boot block 143 may wait for apre-determined period of time, as shown at block 216. Once the timeperiod has been expired, the boot block 143 may again determine if theBIOS image is loaded into the system RAM 106 in block 214. However, ifthe BIOS image is loaded, the boot block 143 may determine whether theBIOS image is a valid version of the BIOS image, as shown in block 218.The validation may include comparing the CRC, digital signature, hash orother calculated value of the BIOS image with a previously stored value.If the BIOS image is not validated, then the boot block 143 may requestanother BIOS image, as shown in block 206. However, if the BIOS image isvalidated, then the execution of the boot process is transferred fromthe boot block 143 to the shadow BIOS 107, as shown in block 220. Atblock 222, the shadow BIOS 107 may continue the boot process. Thecontinued boot process may include performing the POST, configuringsetting for various components, and loading the O/S. Accordingly, theprocess ends at block 224.

Beneficially, using the boot block 143 along with the BMC 111 mayprovide an efficient method of obtaining the BIOS image because the BMC111 may access a variety of locations. As such, the BIOS image may belocated in network systems, such as external memory 48 or another server44 or 46, and/or locally in a flash memory or NVRAM. This providesflexibility in determine the location of the BIOS image. Also, as notedabove, the policy code 174 in the BMC 111 determines the location of theBIOS image. The operation of the policy code is shown in greater detailin FIG. 6 below.

FIG. 6 is a process flow diagram illustrating the use of the policy code174 in the exemplary BMC 111 of FIG. 3 in accordance with embodiments ofthe present invention. The process flow diagram is generally referred toby reference numerals 230. The process flow diagram 230 may be bestunderstood by concurrently viewing FIGS. 1-4. In the process flowdiagram 230, the policy code 174 may receive a request from the bootblock 143 to obtain a specific type or family of BIOS images. The policycode 174 may determine the order and locations to search for the BIOSimage, as set forth below.

The process begins at block 232. At block 234, the policy code 174receives a request from the boot block 143. As noted above, the requestmay include an indication of the version, type, and/or family of theBIOS image. The policy code 174 may then follow a defined policy orsequence to load the BIOS image, which is shown in blocks 236-254. Atblock 236, the policy code 174 may initially attempt to access the BIOSimage via an external memory, such as the external memory 48. Theprocessor 160 executing the policy code 174 may utilize the NIC 184 toaccess the external memory 48, as discussed above. If the policy code174 obtains the BIOS image from the external memory 48, then the BIOSimage is downloaded, as shown in block 238. Then, the BIOS image isvalidated by the boot block 143, as shown in block 240, which is similarto the discussion of block 218 in FIG. 5. However, if the policy code174 does not obtain the BIOS image from the external memory 48, then thepolicy code 174 may log the failure to access the BIOS image from theexternal memory 48, as shown in block 242.

Following the failed attempt, the policy code 174 may access a secondlocation in an attempt to obtain the BIOS image, as shown in blocks 244and 246. At block 244, the policy code 174 may determine whether it canaccess the BIOS image from flash memory, which may be the non-volatilememory 142. The processor 160 executing the policy code 174 may utilizethe ATB unit 176 to access the flash memory via the bus 109, asdiscussed above. If the policy code 174 obtains the BIOS image from theflash memory, then the BIOS image is downloaded, as shown in block 238.However, if the policy code 174 does not obtain the BIOS image from theflash memory, then the policy code 174 may log the failure to access theBIOS image from the flash memory, as shown in block 246.

At blocks 248 and 250, the policy code 174 may access a third locationto obtain the BIOS image. At block 248, the policy code 174 maydetermine whether it can access the BIOS image from BIOS ROM, such asthe BIOS ROM 140. The processor 160 executing the policy code 174 mayagain utilize the ATB 176 to access the BIOS ROM via the bus 109, asdiscussed above. If the policy code 174 obtains the BIOS image from theBIOS ROM, then the BIOS image is downloaded, as shown in block 238.However, if the policy code 174 does not obtain the BIOS image from theBIOS ROM, then the policy code 174 may log the failure to access theBIOS image from the BIOS ROM, as shown in block 250.

If the policy code 174 is unable to access a BIOS image from any of thelocations, then the policy code may notify the boot block 143 regardingfailure to obtain a BIOS image, as shown in block 252. The boot blockmay then request a previous version of the BIOS image be downloaded bythe policy code 174. Accordingly, if a previous version of the BIOSimage is requested by the boot block 143, then the process continues atblock 242. However, if the boot block 143 does not request a previousBIOS image or the BIOS image is downloaded, the process ends at block254.

Because the policy code 174 is accessible on the BMC 111, the policycode 174 may be updated or modified to provide different locations foraccessing the BIOS image. With the policy code 174 managing the accessto the BIOS image, changing the locations to be accessed to obtain theBIOS image may be simplified. That is, boot block 143 does not have tobe modified to provide for a change in locations to be accessed or evenin the policy flow. Further, support personnel may provide an updatedBIOS image to multiple systems by simply updating the BIOS image in acentralized location.

While the invention may be susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, it should be understood that the invention is not intended tobe limited to the particular forms disclosed. Rather, the invention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

1. A method of initializing a system comprising: providing a request,independent from the operation of a system processor, from a boot blockto a baseboard management controller for a basic input/output systemimage; determining a location to access the basic input/output systemimage; obtaining the basic input/output system image from the location;loading the basic input/output system image into system random accessmemory as a shadow basic input/output system image; and transferringcontrol of the initialization process from the boot block to the shadowbasic input/output system image.
 2. The method, as set forth in claim 1,comprising validating the basic input/output system image by the bootblock once the basic input/output system image is loaded into the systemrandom access memory as a shadow BIOS image.
 3. The method, as set forthin claim 1, wherein determining the location to access the basicinput/output system image comprises executing a policy code on aprocessor in the baseboard management controller.
 4. The method, as setforth in claim 1, wherein obtaining the basic input/output system imagefrom the location comprises communicating with an external memory via anetwork to obtain the basic input/output system image.
 5. The method, asset forth in claim 2, comprising loading a second basic input/outputsystem image by the boot block once the first basic input/output systemimage fails validation.
 6. The method, as set forth in claim 1, whereindetermining a location to access the basic input/output system image isaccomplished independent from operation of the system processor.
 7. Themethod, as set forth in claim 1, wherein obtaining the basicinput/output system image from the location is accomplished independentfrom operation of the system processor.
 8. The method, as set forth inclaim 4, wherein the network comprises a wide area network.